1. Field of the Invention
The present invention relates generally to the design of integrated circuits (ICs) and, in particular, to a method of automated IC design based on the use of dynamically created building circuit blocks for achieving specific IC design objectives.
2. Description of the Related Art
Various automatic or semi-automatic design methods for integrated circuits (ICs) have been suggested and/or developed in an attempt to, for example, provide a cost-efficient IC design process. While such previous attempts at automating the IC design process have resulted in some success with respect to containing the cost of IC designs, the quality of the resultant IC designs are compromised as compared to the quality of full custom, handcrafted designs. Thus, despite previously proposed automated and/or semi automated IC design processes, there remains a need for an automated IC design process that can dynamically and efficiently yield IC designs that meet specific design objectives for a given IC design.
IC designs may generally be classified according to the type of circuit building blocks or cells used in the IC design process thereof. Broadly speaking, IC design processes can use either design-specific (i.e., custom) building blocks, or generic (i.e., standard) cells that are pre-defined. Standard cells are often provided as part of one or more libraries of such standard cells. A “custom” IC design process refers to the identification and implementation of the IC design by manual effort/human IC designers, often drawing on years of IC design experience. Often times, at least some of the critical portions of the IC design and the lower levels of design abstraction (e.g., the transistor-level design of blocks) are obtained using manual, custom design processes. The custom design process is labor-intensive, time consuming, and expensive. Custom design processes are prone to design “bugs” that result in long design cycle times. The custom IC design method, however, is typically capable of yielding high quality IC designs well-suited to the design objectives of the IC. This is due to the fact that the implemented IC design is specifically designed, from start to finish, using design-specific circuits and circuit building blocks designed for the subject IC, including all of the design objectives of the IC.
In contrast to manual custom IC design processes, and in response to ever-increasing pressures to reduce the time-to-market cycle time and the IC design cycle time, highly automated IC design processes have been developed. In general, known automatic IC design processes may be classified as, (i) fully pre-fabricated highly programmable component based design processes (e.g., field-programmable gate array (FPGA), etc.), (ii) partially pre-fabricated (e.g., gate array) based design processes: at the completion of the design process, only the metal layers need to fabricated, and (iii) design processes using standard, static pre-defined circuit building blocks (cells) having a pre-defined structure and layout, and fully customizable interconnections between the blocks wherein at the completion of the design process, all components (layers) in the design need to be fabricated from scratch. Among these three general automated design processes, the standard-cell based IC design process typically yields IC designs offering the highest performance, the smallest die size, and the lowest power consumption. Even so, the resultant IC designs achieved using standard cell design processes do not match the IC design quality possible with manual custom IC design processes.
Standard-cell based automated IC design processes use pre-defined logic cells from a library of circuit building blocks for use in the design of the target IC. The standard cells' descriptions are generally available at higher levels of abstraction than the transistor-level (e.g., the gate-level). Standard-cell based IC design processes also typically use computer implemented automated, algorithms to map a given design's functional description onto the given set of library cells. Although usually achieved in shorter design cycle times than manual full custom design processes, the quality of standard-cell based IC designs tends to be poor compared to manual custom designed ICs. This is typically due to the limitations imposed on the design process by the use of a fixed library of pre-defined (static) building blocks that are not uniquely customized to the needs of the IC design.
The proliferation of digital ICs, and the ever-increasing diversity of their applications have prompted the increased use of various metrics or evaluation criteria in measuring the performance and cost of development for ICs. Die size, performance/speed and power consumption have evolved as three of the most commonly used metrics. At the same time, time-to-market (i.e., design cycle time) and expected sales volume have gained importance as two commonly valued metrics. Generally, the time-to-market for IC designs is steadily decreasing for virtually all classes of digital ICs. While the importance of the various metrics varies widely from one IC design to another, two of the most commonly used metrics combinations are (i) performance and power consumption, and (ii) die size and power consumption.
The particular process adopted for a specific IC design application may depend on numerous technical and non-technical issues. As with many of the different IC design formats, there is a need in very large scale integration (VLSI) designs to contain the complexity of the IC design process. The complexity of the IC design process can be addressed depending on the design methodology (i.e., process) used to implement the IC, even complex ICs.
Traditionally, a hierarchical top-down design method is typically used to create an IC. The hierarchical approach allows the system to be specified at a number of levels in a progressive manner from a general description of the target design down to a detailed description of the components comprising the target IC design. Each specified level of the IC design description is derived from the preceding and more generally described higher level. Greater detail is added to the design at each successive lower level. Additionally, use of readily available structures such as ROMs, PLAs and RAMs have been employed to save design time.
Previous automated IC design processes have tried to bridge the performance and design quality gap that exists between the custom and standard-cell design processes by using various methods, including but not limited to, for example, improvements in the performance of a manually/semi-automatically generated design by sizing individual transistors; using greater transistor-level cell layouts once the cell functionalities have been identified; using manual/semi-automated methods for generating transistor-level layout, since traditionally, transistor-level layouts involve extensive manual intervention (typically without regard to conformance to the highly automated nature of standard-cell based design flows); using new/improved methods for selecting better-sized library elements (constraints/objective-driven methods, for example delay-model driven sizing methods); using new/improved methods for creating unique (possibly dynamic and possibly capable of implementing universal logic) pre-characterized transistor logic elements; and using new/improved methods for adding variously sized library elements to a pre-defined existing library.
However, despite the efforts to bridge the performance and design quality gap between manual IC designs, and IC designs generated by automated design processes there remains a significant shortfall in the quality of automatically generated IC designs.
The present inventors have realized sources of deficiency in existing automated design processes. These include the static nature of the certain fundamental aspects of such automated IC design methods.